Branch: dev/master
Commit: a5dc30e0
Date: 2025-07-15 18:10
Operator | Target | Frequency | Tests | Generation | Simulation | % | Status | Last Changed |
---|---|---|---|---|---|---|---|---|
▼FP2Fix | 18 | 18 | 18 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 6 | 6 | 6 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 6 | 6 | 6 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 6 | 6 | 6 | 100% | = | n/a | |
▼FPAdd | 27 | 27 | 27 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 9 | 9 | 9 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 9 | 9 | 9 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 9 | 9 | 9 | 100% | = | n/a | |
▼FPComparator | 9 | 9 | 9 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
▼FPConstDiv | 18 | 18 | 18 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 6 | 6 | 6 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 6 | 6 | 6 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 6 | 6 | 6 | 100% | = | n/a | |
▼FPConstMult | 27 | 27 | 27 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 9 | 9 | 9 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 9 | 9 | 9 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 9 | 9 | 9 | 100% | = | n/a | |
▼FPDiv | 9 | 9 | 9 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
▼FPExp | 9 | 9 | 8 | 89% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 2 | 67% | = | n/a | |
▼FPLog | 9 | 9 | 9 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
▼FPMult | 9 | 9 | 9 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
▼FPPow | 18 | 18 | 15 | 83% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | ||
DummyFPGA | 0 MHz | 6 | 6 | 6 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 6 | 6 | 6 | 100% | PASS! | a5dc30e0 (2025-07-15 15:52:46 +0000): PASS! | |
Zynq7000 | 100 MHz | 6 | 6 | 3 | 50% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
▼FPSqrt | 9 | 9 | 9 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
▼Fix2DNorm | 72 | 69 | 57 | 79% | = | n/a | ||
DummyFPGA | 0 MHz | 24 | 24 | 24 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 24 | 24 | 24 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 24 | 21 | 9 | 38% | = | n/a | |
▼Fix3DNorm | 72 | 71 | 57 | 79% | = | n/a | ||
DummyFPGA | 0 MHz | 24 | 24 | 24 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 24 | 24 | 24 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 24 | 23 | 9 | 38% | = | n/a | |
▼FixFIR | 36 | 36 | 36 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 12 | 12 | 12 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
▼FixFunctionByMultipartiteTable | 24 | 18 | 18 | 75% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | ||
DummyFPGA | 0 MHz | 8 | 6 | 6 | 75% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
DummyFPGA | 100 MHz | 8 | 6 | 6 | 75% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
Zynq7000 | 100 MHz | 8 | 6 | 6 | 75% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
▼FixFunctionByPiecewisePoly | 24 | 24 | 24 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 8 | 8 | 8 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
▼FixFunctionBySimplePoly | 24 | 24 | 24 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 8 | 8 | 8 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
▼FixFunctionByTable | 24 | 24 | 24 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 8 | 8 | 8 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
▼FixIIR | 3 | 3 | 3 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 1 | 1 | 1 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 1 | 1 | 1 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 1 | 1 | 1 | 100% | = | n/a | |
▼FixMultAdd | 96 | 96 | 60 | 62% | = | n/a | ||
DummyFPGA | 0 MHz | 32 | 32 | 20 | 62% | = | n/a | |
DummyFPGA | 100 MHz | 32 | 32 | 20 | 62% | = | n/a | |
Zynq7000 | 100 MHz | 32 | 32 | 20 | 62% | = | n/a | |
▼FixMultiAdder | 24 | 24 | 24 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 8 | 8 | 8 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 8 | 8 | 8 | 100% | = | n/a | |
▼FixResize | 240 | 240 | 240 | 100% | n/a | n/a | ||
DummyFPGA | 0 MHz | 80 | 80 | 80 | 100% | n/a | n/a | |
DummyFPGA | 100 MHz | 80 | 80 | 80 | 100% | n/a | n/a | |
Zynq7000 | 100 MHz | 80 | 80 | 80 | 100% | n/a | n/a | |
▼FixSinCos | 36 | 36 | 36 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 12 | 12 | 12 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
▼FixSumOfSquares | 42 | 42 | 36 | 86% | = | n/a | ||
DummyFPGA | 0 MHz | 14 | 14 | 14 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 14 | 14 | 14 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 14 | 14 | 8 | 57% | = | n/a | |
▼IEEEFPExp | 9 | 9 | 8 | 89% | = | n/a | ||
DummyFPGA | 0 MHz | 3 | 3 | 3 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 3 | 3 | 3 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 3 | 3 | 2 | 67% | = | n/a | |
▼IntAddSub | 12 | 10 | 9 | 75% | = | n/a | ||
DummyFPGA | 0 MHz | 4 | 4 | 4 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 4 | 4 | 4 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 4 | 2 | 1 | 25% | = | n/a | |
▼IntAdder | 30 | 30 | 30 | 100% | = | 2f74b78 (2025-07-03 10:59:13 +0200): PASS! | ||
DummyFPGA | 0 MHz | 10 | 10 | 10 | 100% | = | 2f74b78 (2025-07-03 10:59:13 +0200): PASS! | |
DummyFPGA | 100 MHz | 10 | 10 | 10 | 100% | = | 2f74b78 (2025-07-03 10:59:13 +0200): PASS! | |
Zynq7000 | 100 MHz | 10 | 10 | 10 | 100% | = | 2f74b78 (2025-07-03 10:59:13 +0200): PASS! | |
▼IntConstDiv | 15 | 15 | 15 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 5 | 5 | 5 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 5 | 5 | 5 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 5 | 5 | 5 | 100% | = | n/a | |
▼IntConstMult | 138 | 138 | 138 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 46 | 46 | 46 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 46 | 46 | 46 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 46 | 46 | 46 | 100% | = | n/a | |
▼IntFIRTransposed | 21 | 21 | 21 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 7 | 7 | 7 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 7 | 7 | 7 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 7 | 7 | 7 | 100% | = | n/a | |
▼IntMultiplier | 192 | 192 | 180 | 94% | = | n/a | ||
DummyFPGA | 0 MHz | 64 | 64 | 64 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 64 | 64 | 64 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 64 | 64 | 52 | 81% | = | n/a | |
▼IntSquarer | 168 | 168 | 149 | 89% | = | n/a | ||
DummyFPGA | 0 MHz | 56 | 56 | 56 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 56 | 56 | 56 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 56 | 56 | 37 | 66% | = | n/a | |
▼Normalizer | 36 | 36 | 36 | 100% | = | n/a | ||
DummyFPGA | 0 MHz | 12 | 12 | 12 | 100% | = | n/a | |
DummyFPGA | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
Zynq7000 | 100 MHz | 12 | 12 | 12 | 100% | = | n/a | |
▼Total | 1500 | 1488 | 1383 | 92% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | ||
DummyFPGA | 0 MHz | 500 | 498 | 486 | 97% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
DummyFPGA | 100 MHz | 500 | 498 | 486 | 97% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
Zynq7000 | 100 MHz | 500 | 492 | 411 | 82% | ↑ | a5dc30e0 (2025-07-15 15:52:46 +0000): ↑ | |
▼BitheapTest | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Compressor | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼DAGOperator | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Exp | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Fix2FP | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixAtan2 | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixComplexAdder | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixComplexKCM | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixComplexR2Butterfly | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixFFTFullyPA | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixFixConstMult | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixHalfSine | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixIIRShiftAdd | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixRealConstMult | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixRealKCM | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixRealShiftAdd | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixRootRaisedCosine | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixSOPC | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixSOPCfull | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼FixSinOrCos | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼GenericLut | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼GenericMux | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IEEEFPAdd | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IEEEFPFMA | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼InputIEEE | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntComparator | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntConstantComparator | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntDualAddSub | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntMultiAdder | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntSquarerLUT | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼IntelTernaryAdder | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼LZOC | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼LZOC3 | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼OutputIEEE | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PIF2Fix | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PIF2Posit | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PIFAdd | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Posit2FP | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Posit2PIF | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Posit2Posit | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PositAdd | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PositExp | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼PositFunctionByTable | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼RegisterSandwich | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼RowAdder | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼SRTDivNbBitsMin | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼ShiftReg | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼Shifter | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼SortWrapper | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼SortingNetwork | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼TaoSort | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼TestBench | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
▼TutorialOperator | 0 | 0 | 0 | 0% | = | n/a | ||
DummyFPGA | 0 MHz | 0 | 0 | 0 | 0% | = | n/a | |
DummyFPGA | 100 MHz | 0 | 0 | 0 | 0% | = | n/a | |
Zynq7000 | 100 MHz | 0 | 0 | 0 | 0% | = | n/a |