FloPoCo autotest results

Branch: dev/master

Commit: dad413e

Date: 2026-02-04 15:12

Operator	Target	Frequency	Tests	Generation	Simulation	%	Status	Last Changed
▼FP2Fix			18	18	18	100%	=	n/a
	DummyFPGA	0 MHz	6	6	6	100%	=	n/a
	DummyFPGA	100 MHz	6	6	6	100%	=	n/a
	Zynq7000	100 MHz	6	6	6	100%	=	n/a
▼FPAdd			27	27	27	100%	=	n/a
	DummyFPGA	0 MHz	9	9	9	100%	=	n/a
	DummyFPGA	100 MHz	9	9	9	100%	=	n/a
	Zynq7000	100 MHz	9	9	9	100%	=	n/a
▼FPComparator			9	9	9	100%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	3	100%	=	n/a
▼FPConstDiv			18	18	18	100%	=	n/a
	DummyFPGA	0 MHz	6	6	6	100%	=	n/a
	DummyFPGA	100 MHz	6	6	6	100%	=	n/a
	Zynq7000	100 MHz	6	6	6	100%	=	n/a
▼FPConstMult			27	27	27	100%	=	n/a
	DummyFPGA	0 MHz	9	9	9	100%	=	n/a
	DummyFPGA	100 MHz	9	9	9	100%	=	n/a
	Zynq7000	100 MHz	9	9	9	100%	=	n/a
▼FPDiv			9	9	9	100%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	3	100%	=	n/a
▼FPExp			9	9	8	89%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	2	67%	=	n/a
▼FPLog			9	9	9	100%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	3	100%	=	n/a
▼FPMult			9	9	9	100%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	3	100%	=	n/a
▼FPPow			18	18	15	83%	=	a5dc30e0 (2025-07-15 15:52:46 +0000): ↑
	DummyFPGA	0 MHz	6	6	6	100%	=	n/a
	DummyFPGA	100 MHz	6	6	6	100%	=	a5dc30e0 (2025-07-15 15:52:46 +0000): PASS!
	Zynq7000	100 MHz	6	6	3	50%	=	a5dc30e0 (2025-07-15 15:52:46 +0000): ↑
▼FPSqrt			9	9	9	100%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	3	100%	=	n/a
▼Fix2DNorm			72	72	72	100%	PASS!	dad413e (2026-02-04 13:54:34 +0000): PASS!
	DummyFPGA	0 MHz	24	24	24	100%	=	n/a
	DummyFPGA	100 MHz	24	24	24	100%	=	n/a
	Zynq7000	100 MHz	24	24	24	100%	PASS!	dad413e (2026-02-04 13:54:34 +0000): PASS!
▼Fix2FP			24	24	24	100%	=	6aa0c95 (2026-02-03 17:25:59 +0100): PASS!
	DummyFPGA	0 MHz	8	8	8	100%	=	6aa0c95 (2026-02-03 17:25:59 +0100): PASS!
	DummyFPGA	100 MHz	8	8	8	100%	=	6aa0c95 (2026-02-03 17:25:59 +0100): PASS!
	Zynq7000	100 MHz	8	8	8	100%	=	6aa0c95 (2026-02-03 17:25:59 +0100): PASS!
▼Fix3DNorm			72	72	72	100%	PASS!	dad413e (2026-02-04 13:54:34 +0000): PASS!
	DummyFPGA	0 MHz	24	24	24	100%	=	n/a
	DummyFPGA	100 MHz	24	24	24	100%	=	n/a
	Zynq7000	100 MHz	24	24	24	100%	PASS!	dad413e (2026-02-04 13:54:34 +0000): PASS!
▼FixFIR			36	36	36	100%	=	n/a
	DummyFPGA	0 MHz	12	12	12	100%	=	n/a
	DummyFPGA	100 MHz	12	12	12	100%	=	n/a
	Zynq7000	100 MHz	12	12	12	100%	=	n/a
▼FixFunctionByMultipartiteTable			24	24	24	100%	=	583d985 (2025-11-06 13:37:10 +0000): PASS!
	DummyFPGA	0 MHz	8	8	8	100%	=	583d985 (2025-11-06 13:37:10 +0000): PASS!
	DummyFPGA	100 MHz	8	8	8	100%	=	583d985 (2025-11-06 13:37:10 +0000): PASS!
	Zynq7000	100 MHz	8	8	8	100%	=	583d985 (2025-11-06 13:37:10 +0000): PASS!
▼FixFunctionByPiecewisePoly			24	24	24	100%	=	n/a
	DummyFPGA	0 MHz	8	8	8	100%	=	n/a
	DummyFPGA	100 MHz	8	8	8	100%	=	n/a
	Zynq7000	100 MHz	8	8	8	100%	=	n/a
▼FixFunctionBySimplePoly			24	24	24	100%	=	n/a
	DummyFPGA	0 MHz	8	8	8	100%	=	n/a
	DummyFPGA	100 MHz	8	8	8	100%	=	n/a
	Zynq7000	100 MHz	8	8	8	100%	=	n/a
▼FixFunctionByTable			24	24	24	100%	=	n/a
	DummyFPGA	0 MHz	8	8	8	100%	=	n/a
	DummyFPGA	100 MHz	8	8	8	100%	=	n/a
	Zynq7000	100 MHz	8	8	8	100%	=	n/a
▼FixIIR			3	3	3	100%	=	n/a
	DummyFPGA	0 MHz	1	1	1	100%	=	n/a
	DummyFPGA	100 MHz	1	1	1	100%	=	n/a
	Zynq7000	100 MHz	1	1	1	100%	=	n/a
▼FixMultAdd			96	96	72	75%	=	381c6c2 (2026-01-09 18:18:09 +0100): ↑
	DummyFPGA	0 MHz	32	32	24	75%	=	381c6c2 (2026-01-09 18:18:09 +0100): ↑
	DummyFPGA	100 MHz	32	32	24	75%	=	381c6c2 (2026-01-09 18:18:09 +0100): ↑
	Zynq7000	100 MHz	32	32	24	75%	=	381c6c2 (2026-01-09 18:18:09 +0100): ↑
▼FixMultiAdder			24	24	24	100%	=	n/a
	DummyFPGA	0 MHz	8	8	8	100%	=	n/a
	DummyFPGA	100 MHz	8	8	8	100%	=	n/a
	Zynq7000	100 MHz	8	8	8	100%	=	n/a
▼FixResize			240	240	240	100%	=	n/a
	DummyFPGA	0 MHz	80	80	80	100%	=	n/a
	DummyFPGA	100 MHz	80	80	80	100%	=	n/a
	Zynq7000	100 MHz	80	80	80	100%	=	n/a
▼FixSinCos			36	36	36	100%	=	n/a
	DummyFPGA	0 MHz	12	12	12	100%	=	n/a
	DummyFPGA	100 MHz	12	12	12	100%	=	n/a
	Zynq7000	100 MHz	12	12	12	100%	=	n/a
▼FixSumOfSquares			42	42	42	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
	DummyFPGA	0 MHz	14	14	14	100%	=	n/a
	DummyFPGA	100 MHz	14	14	14	100%	=	n/a
	Zynq7000	100 MHz	14	14	14	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
▼IEEEFPExp			9	9	8	89%	=	n/a
	DummyFPGA	0 MHz	3	3	3	100%	=	n/a
	DummyFPGA	100 MHz	3	3	3	100%	=	n/a
	Zynq7000	100 MHz	3	3	2	67%	=	n/a
▼IntAddSub			12	12	12	100%	=	d2a034e (2026-01-07 17:17:51 +0100): PASS!
	DummyFPGA	0 MHz	4	4	4	100%	=	n/a
	DummyFPGA	100 MHz	4	4	4	100%	=	n/a
	Zynq7000	100 MHz	4	4	4	100%	=	d2a034e (2026-01-07 17:17:51 +0100): PASS!
▼IntAdder			30	30	30	100%	=	2f74b78 (2025-07-03 10:59:13 +0200): PASS!
	DummyFPGA	0 MHz	10	10	10	100%	=	2f74b78 (2025-07-03 10:59:13 +0200): PASS!
	DummyFPGA	100 MHz	10	10	10	100%	=	2f74b78 (2025-07-03 10:59:13 +0200): PASS!
	Zynq7000	100 MHz	10	10	10	100%	=	2f74b78 (2025-07-03 10:59:13 +0200): PASS!
▼IntConstDiv			15	15	15	100%	=	n/a
	DummyFPGA	0 MHz	5	5	5	100%	=	n/a
	DummyFPGA	100 MHz	5	5	5	100%	=	n/a
	Zynq7000	100 MHz	5	5	5	100%	=	n/a
▼IntConstMult			138	138	138	100%	=	n/a
	DummyFPGA	0 MHz	46	46	46	100%	=	n/a
	DummyFPGA	100 MHz	46	46	46	100%	=	n/a
	Zynq7000	100 MHz	46	46	46	100%	=	n/a
▼IntFIRTransposed			21	21	21	100%	=	n/a
	DummyFPGA	0 MHz	7	7	7	100%	=	n/a
	DummyFPGA	100 MHz	7	7	7	100%	=	n/a
	Zynq7000	100 MHz	7	7	7	100%	=	n/a
▼IntMultiplier			192	192	192	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
	DummyFPGA	0 MHz	64	64	64	100%	=	n/a
	DummyFPGA	100 MHz	64	64	64	100%	=	n/a
	Zynq7000	100 MHz	64	64	64	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
▼IntSquarer			168	168	168	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
	DummyFPGA	0 MHz	56	56	56	100%	=	n/a
	DummyFPGA	100 MHz	56	56	56	100%	=	n/a
	Zynq7000	100 MHz	56	56	56	100%	=	79212ea (2026-01-06 10:58:09 +0100): PASS!
▼Normalizer			36	36	36	100%	=	n/a
	DummyFPGA	0 MHz	12	12	12	100%	=	n/a
	DummyFPGA	100 MHz	12	12	12	100%	=	n/a
	Zynq7000	100 MHz	12	12	12	100%	=	n/a
▼OneHotDecoder			66	66	66	100%	=	n/a
	DummyFPGA	0 MHz	22	22	22	100%	=	n/a
	DummyFPGA	100 MHz	22	22	22	100%	=	n/a
	Zynq7000	100 MHz	22	22	22	100%	=	n/a
▼ThermometerDecoder			66	66	66	100%	=	n/a
	DummyFPGA	0 MHz	22	22	22	100%	=	n/a
	DummyFPGA	100 MHz	22	22	22	100%	=	n/a
	Zynq7000	100 MHz	22	22	22	100%	=	n/a
▼Total			1656	1656	1627	98%	↑	dad413e (2026-02-04 13:54:34 +0000): ↑
	DummyFPGA	0 MHz	552	552	544	99%	=	6aa0c95 (2026-02-03 17:25:59 +0100): ↑
	DummyFPGA	100 MHz	552	552	544	99%	=	6aa0c95 (2026-02-03 17:25:59 +0100): ↑
	Zynq7000	100 MHz	552	552	539	98%	↑	dad413e (2026-02-04 13:54:34 +0000): ↑
▼BitheapTest			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Compressor			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼DAGOperator			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Exp			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixAtan2			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixComplexAdder			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixComplexKCM			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixComplexR2Butterfly			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixFFTFullyPA			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixFixConstMult			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixHalfSine			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixIIRShiftAdd			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixRealConstMult			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixRealKCM			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixRealShiftAdd			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixRootRaisedCosine			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixSOPC			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixSOPCfull			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼FixSinOrCos			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼GenericLut			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼GenericMux			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IEEEFPAdd			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IEEEFPFMA			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼InputIEEE			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntComparator			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntConstantComparator			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntDualAddSub			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntMultiAdder			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntSquarerLUT			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼IntelTernaryAdder			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼LZOC			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼LZOC3			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼OutputIEEE			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PIF2Fix			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PIF2Posit			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PIFAdd			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Posit2FP			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Posit2PIF			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Posit2Posit			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PositAdd			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PositExp			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼PositFunctionByTable			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼RegisterSandwich			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼RowAdder			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼SRTDivNbBitsMin			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼ShiftReg			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼Shifter			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼SortWrapper			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼SortingNetwork			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼TaoSort			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼TestBench			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a
▼TutorialOperator			0	0	0	0%	=	n/a
	DummyFPGA	0 MHz	0	0	0	0%	=	n/a
	DummyFPGA	100 MHz	0	0	0	0%	=	n/a
	Zynq7000	100 MHz	0	0	0	0%	=	n/a