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| [76] | Florent de Dinechin and Martin Kumm. Application-Specific Arithmetic. Springer, 2024. [ bib | http ] |
| [75] | Anastasia Volkova, Rémi Garcia, Florent de Dinechin, and Martin Kumm. Hardware-optimal digital FIR filters: one ILP to rule them all and in faithfulness bind them. In Asilomar Conference on Signals, Systems, and Computers, February 2023. [ bib | http ] |
| [74] | Martin Hardieck, Tobias Habermann, Fabian Wagner, Martin Kumm, Michael Mecik, and Peter Zipf. More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. In IEEE International Symposium on Circuits and Systems (ISCAS), volume 28, pages 115--128, 2023. [ bib | DOI ] |
| [73] | Andreas Böttcher and Martin Kumm. Towards globally optimal design of multipliers for FPGAs. IEEE Transactions on Computers, 72(5):1261 -- 1273, 2023. [ bib | DOI ] |
| [72] | Orégane Desrentes and Florent de Dinechin. Using integer linear programming for correctly rounded multipartite architectures. In International Conference on Field Programmable Technology, December 2022. [ bib | http | .pdf ] |
| [71] | Andreas Böttcher, Martin Kumm, and Florent de Dinechin. Resource Optimal Squarers for FPGAs. In International Conference on Field-Programmable Logic and Applications (FPL). IEEE, August 2022. [ bib | DOI | http | .pdf ] |
| [70] | Remi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, and Jonas Kuhle. Hardware-aware design of multiplierless second-order IIR filters with minimum adders. IEEE Transactions on Signal Processing, 70:1673 -- 1686, 2022. [ bib | DOI ] |
| [69] | Tobias Habermann, Jonas Kühle, Martin Kumm, and Anastasia Volkova. Hardware-aware quantization for multiplierless neural network controllers. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pages 1---5, 2022. [ bib | http ] |
| [68] | Andreas Böttcher, Martin Kumm, and Florent de Dinechin. Resource optimal truncated multipliers for FPGAs. In IEEE Symposium on Computer Arithmetic (ARITH), pages 102--109, 2021. [ bib | DOI | http ] |
| [67] | Lukas Sommer, Lukas Weber, M Kumm, and Andreas Koch. Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. In International Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 75--83. IEEE, 2020. [ bib ] |
| [66] | Andreas Böttcher, Keanu Kullmann, and Martin Kumm. Heuristics for the Design of Large Multipliers for FPGAs. In IEEE Symposium on Computer Arithmetic (ARITH), 2020. [ bib ] |
| [65] | Raul Murillo, Alberto A. Del Barrio, and Guillermo Botella. Customized posit adders and multipliers using the FloPoCo core generator. In 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020. [ bib ] |
| [64] | Florent de Dinechin, Silviu-Ioan Filip, Luc Forget, and Martin Kumm. Table-based versus shift-and-add constant multipliers for FPGAs. In 26th IEEE Symposium of Computer Arithmetic (ARITH-26), June 2019. [ bib | http ] |
| [63] | Florent de Dinechin. Reflections on 10 years of FloPoCo. In 26th IEEE Symposium of Computer Arithmetic (ARITH-26), June 2019. [ bib | http ] |
| [62] | Anastasia Volkova, Matei Istoan, Florent de Dinechin, and Thibault Hilaire. Towards hardware IIR filters computing just right: Direct form I case study. IEEE Transactions on Computers, 68(4), April 2019. [ bib | .pdf ] |
| [61] | Martin Hardieck, M Kumm, Konrad Möller, and Peter Zipf. Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pages 43--52. ACM, February 2019. [ bib ] |
| [60] | Mario Garrido, Konrad Möller, and Martin Kumm. World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019. [ bib ] |
| [59] | Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf. Karatsuba with rectangular multipliers for FPGAs. In 25th IEEE Symposium of Computer Arithmetic (ARITH-25), June 2018. Best paper award. [ bib | .pdf ] |
| [58] | Martin Hardieck, M Kumm, Patrick Sittel, and Peter Zipf. Constant Matrix Multiplication with Ternary Adders. In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 85--88. IEEE, 2018. [ bib ] |
| [57] | Martin Kumm, Oscar Gustafsson, Mario Garrido, and Peter Zipf. Optimal Single Constant Multiplication using Ternary Adders. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(7):928--932, 2018. [ bib ] |
| [56] | Martin Kumm and Johannes Kappauf. Advanced Compressor Tree Synthesis for FPGAs. IEEE Transactions on Computers, 67(8):1078--1091, 2018. [ bib ] |
| [55] | Nicolas Brisebarre, George Constantinides, Miloš Ercezovac, Silviu-Ioan Filip, Matei Iştoan, and Jean-Michel Muller. A high throughput polynomial and rational function approximations evaluator. In 25th Symposium on Computer Arithmetic (ARITH), pages 99--106. IEEE, 2018. [ bib ] |
| [54] | Martin Kumm, Johannes Kappauf, Matei Istoan, and Peter Zipf. Resource optimal design of large multipliers for FPGAs. In 24th Symposium of Computer Arithmetic. IEEE, July 2017. [ bib ] |
| [53] | Matei Istoan and Florent de Dinechin. Automating the pipeline of arithmetic datapaths. In DATE 2017, Lausanne, Switzerland, March 2017. [ bib | http | .pdf ] |
| [52] | M Kumm, Johannes Kappauf, Matei Istoan, and Peter Zipf. Optimal Design of Large Multipliers for FPGAs. In IEEE Symposium on Computer Arithmetic (ARITH), pages 131--138, 2017. [ bib ] |
| [51] | Konrad Möller, Martin Kumm, Marco Kleinlein, and Peter Zipf. Reconfigurable Constant Multiplication for FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(6):927--937, 2017. [ bib ] |
| [50] | Martin Kumm, Martin Hardieck, and Peter Zipf. Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Transactions on Computers, 66(12):2072--2080, 2017. [ bib ] |
| [49] | H. Fatih Ugurdag, Florent de Dinechin, Y. Serhan Gener, Sezer Gören, and Laurent-Stéphane Didier. Hardware division by small integer constants. IEEE Transactions on Computers, 2017. [ bib ] |
| [48] | H. Fatih Ugurdag, Anil Bayram, Vecdi Emre Levent, and Sezer Gören. Efficient combinational circuits for division by small integer constants. In 23nd Symposium of Computer Arithmetic. IEEE, June 2016. [ bib ] |
| [47] | M Kumm, Marco Kleinlein, and Peter Zipf. Efficient Sum of Absolute Difference Computation on FPGAs. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 1--4, Lausanne, 2016. [ bib ] |
| [46] | Martin Kumm. Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays. PhD thesis, Springer Wiesbaden, Wiesbaden, October 2015. [ bib ] |
| [45] | Florent de Dinechin and Matei Istoan. Hardware implementations of fixed-point Atan2. In 22nd Symposium of Computer Arithmetic. IEEE, June 2015. [ bib | .pdf ] |
| [44] | M Kumm, Shahid Abbas, and Peter Zipf. An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. In IEEE Symposium on Computer Arithmetic (ARITH), pages 18--25, 2015. [ bib ] |
| [43] | David B. Thomas. A general-purpose method for faithfully rounded floating-point function approximation in FPGAs. In 22d Symposium on Computer Arithmetic. IEEE, 2015. [ bib | .pdf ] |
| [42] | Konrad Möller, Martin Kumm, Marco Kleinlein, and Peter Zipf. Pipelined reconfigurable multiplication with constants on FPGAs. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 1--6. IEEE, 2014. [ bib ] |
| [41] | Martin Kumm and Peter Zipf. Pipelined Compressor Tree Optimization Using Integer Linear Programming. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 1--8. IEEE, 2014. [ bib ] |
| [40] | Martin Kumm and Peter Zipf. Efficient High Speed Compression Trees on Xilinx FPGAs. In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014. [ bib ] |
| [39] | Florent de Dinechin, Matei Istoan, and Abdelbassat Massouri. Sum-of-product architectures computing just right. In Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2014. [ bib | http | .pdf ] |
| [38] | Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, and Bogdan Popa. Arithmetic core generation using bit heaps. In Field-Programmable Logic and Applications, September 2013. [ bib | .pdf ] |
| [37] | David B. Thomas and Wayne Luk. The LUT-SR family of uniform random number generators for FPGA architectures. IEEE Transactions on VLSI Systems, 21(4), April 2013. [ bib ] |
| [36] | Florent de Dinechin and Bogdan Pasca. High-Performance Computing using FPGAs, chapter Reconfigurable Arithmetic for High Performance Computing, pages 631--664. Springer, 2013. [ bib | .pdf ] |
| [35] | Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, and Bogdan Pasca. Floating-point exponentiation units for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 2013. [ bib | http | .pdf ] |
| [34] | Florent de Dinechin, Matei Istoan, and Guillaume Sergent. Fixed-point trigonometric functions on FPGAs. SIGARCH Computer Architecture News, 41(5):83--88, 2013. [ bib | .pdf ] |
| [33] | David B. Thomas. Parallel generation of Gaussian random numbers using the Table-Hadamard transform. In FPGAs for custom computing machines, 2013. [ bib | .pdf ] |
| [32] | Florent de Dinechin and Laurent-Stéphane Didier. Table-based division by small integer constants. In Applied Reconfigurable Computing, pages 53--63, Hong Kong, March 2012. [ bib | .pdf ] |
| [31] | Florent de Dinechin. Multiplication by rational constants. IEEE Transactions on Circuits and Systems, II, 52(2):98--102, February 2012. [ bib | http | .pdf ] |
| [30] | Martin Kumm and Peter Zipf. Hybrid Multiple Constant Multiplication for FPGAs. In IEEE International Conference on Electronics, Circuits and Systems, (ICECS), pages 556--559, 2012. [ bib ] |
| [29] | Martin Kumm, Katharina Liebisch, and Peter Zipf. Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision. In IEEE International Conference on Field Programmable Logic and Application (FPL), pages 255--261, 2012. [ bib ] |
| [28] | Bogdan Mihai Pasca. High-performance floating-point computing on reconfigurable circuits. Theses, Ecole normale supérieure de lyon - ENS LYON, September 2011. [ bib | http | .pdf ] |
| [27] | Florent de Dinechin. The arithmetic operators you will never see in a microprocessor. In 20th Symposium on Computer Arithmetic, pages pp 189--190. IEEE, July 2011. [ bib | .pdf ] |
| [26] | Florent de Dinechin and Bogdan Pasca. Designing custom arithmetic data paths with FloPoCo. IEEE Design & Test of Computers, 28(4):18--27, July 2011. [ bib | .pdf ] |
| [25] | Hong Diep Nguyen, Bogdan Pasca, and Thomas B. Preußer. FPGA-specific arithmetic optimizations of short-latency adders. In Field Programmable Logic and Applications. IEEE, 2011. [ bib | http ] |
| [24] | Florent de Dinechin and Bogdan Pasca. Floating-point exponential functions for DSP-enabled FPGAs. In Field Programmable Technologies, pages 110--117, December 2010. [ bib | .pdf ] |
| [23] | Alvaro Vazquez and Florent de Dinechin. Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. In Field-Programmable Technology, pages 126--133, December 2010. [ bib | .pdf ] |
| [22] | Florent de Dinechin, Hong Diep Nguyen, and Bogdan Pasca. Pipelined FPGA adders. In Field-Programmable Logic and Applications, pages 422--427, 2010. [ bib | .pdf ] |
| [21] | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Multiplicative square root algorithms for FPGAs. In Field-Programmable Logic and Applications, pages 574--577, 2010. [ bib | .pdf ] |
| [20] | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. In Highly-Efficient Accelerators and Reconfigurable Technologies, 2010. [ bib | .pdf ] |
| [19] | Florent de Dinechin, Mioara Joldes, and Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. IEEE, 2010. [ bib | .pdf ] |
| [18] | Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. Lip research report rr2010-22, ENS-Lyon, 2010. [ bib | http ] |
| [17] | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. ACM SIGARCH Computer Architecture News, 38:73--79, 2010. [ bib | http | .pdf ] |
| [16] | P. D. Vouzis, Caroline Collange, and Mark G. Arnold. A novel cotransformation for LNS subtraction. Journal of Signal Processing Systems, 58(1):29--40, 2010. [ bib ] |
| [15] | Florent de Dinechin and Bogdan Pasca. Large multipliers with fewer DSP blocks. In Field Programmable Logic and Applications, pages 250--255. IEEE, August 2009. [ bib | .pdf ] |
| [14] | Florent de Dinechin, Cristian Klein, and Bogdan Pasca. Generating high-performance custom floating-point pipelines. In Field Programmable Logic and Applications, pages 59--64. IEEE, August 2009. [ bib | .pdf ] |
| [13] | Jérémie Detrey and Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques, 27(6):673--698, 2008. [ bib ] |
| [12] | Florent de Dinechin, Bogdan Pasca, Octavian Creţ, and Radu Tudoran. An FPGA-specific approach to floating-point accumulation and sum-of-products. In Field-Programmable Technologies, pages 33--40. IEEE, 2008. [ bib | .pdf ] |
| [11] | Nicolas Brisebarre, Florent de Dinechin, and Jean-Michel Muller. Integer and floating-point constant multipliers for FPGAs. In Application-specific Systems, Architectures and Processors, pages 239--244. IEEE, 2008. [ bib | .pdf ] |
| [10] | Jérémie Detrey. Arithmétiques réelles sur FPGA : virgule fixe, virgule flottante et système logarithmique. PhD thesis, École Normale Supérieure de Lyon, Lyon, France, January 2007. [ bib | .pdf ] |
| [9] | Jérémie Detrey and Florent de Dinechin. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, 31(8):537--545, 2007. [ bib | DOI | .pdf ] |
| [8] | Jérémie Detrey, Florent de Dinechin, and Xavier Pujol. Return of the hardware floating-point elementary function. In 18th Symposium on Computer Arithmetic, pages 161--168. IEEE, 2007. [ bib | .pdf ] |
| [7] | Jérémie Detrey and Florent de Dinechin. Floating-point trigonometric functions for FPGAs. In Field-Programmable Logic and Applications, pages 29--34. IEEE, 2007. [ bib | .pdf ] |
| [6] | Florent de Dinechin, Jérémie Detrey, Octavian Creţ, and Radu Tudoran. When FPGAs are better at floating-point than microprocessors. Technical Report ensl-00174627, ÉNS Lyon, 2007. http://prunel.ccsd.cnrs.fr/ensl-00174627. [ bib ] |
| [5] | Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques. Précision, performance et validation. PhD thesis, 2007. [ bib | .pdf ] |
| [4] | Jérémie Detrey and Florent de Dinechin. A parameterized floating-point exponential function for FPGAs. In Field-Programmable Technology. IEEE, 2005. [ bib | .pdf ] |
| [3] | Jérémie Detrey and Florent de Dinechin. A parameterizable floating-point logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE, 2005. [ bib | .pdf ] |
| [2] | Jérémie Detrey and Florent de Dinechin. Table-based polynomials for fast hardware function evaluation. In Application-specific Systems, Architectures and Processors, pages 328--333. IEEE, 2005. [ bib | .pdf ] |
| [1] | Florent de Dinechin and Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, 54(3):319--330, 2005. [ bib | .pdf ] |
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