FloPoCo

Circuits computing just right

FPGA arithmetic the way it should be

FloPoCo is a generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only).

The first motto of FloPoCo is that arithmetic on FPGAs should not mimick processor arithmetic. By designing radically new operators, one may obtain more accurate results with less hardware in less time. This thesis was first detailed in this document.

The second motto of FloPoCo is to enable computing just right. All FloPoCo operators are

1. fully parameterized in precision, so that your application may use just the precision it needs, and
2. accurate to the last bit, so that your wires don't carry meaningless noise.

Internally, FloPoCo operators are carefully designed to ensure that no bit is computed that is not useful to the final result.

All this is the subject of our book. Click on it for details.

FloPoCo is not a library of operators, but a generator of operators written in C++. It inputs operator specifications, and outputs synthesizable VHDL.

While waiting for the next release (we are working on it, honest) you may want to read the 2-page paper Reflections on 10 years of FloPoCo, or look at the slides presented at our FPL 2024 keynote.

Distribution

FloPoCo is open-source, contributions are welcome!

FloPoCo is distributed under the FloPoCo license. It is a modified AGPL, so that the code generated by FloPoCo is itself available under LGPL.

Do not hesitate to contact us to negociate a commercial license.

Documentation

Installation instructions (Linux, Mac, Windows).

List of operators with their command-line syntax

• For current git version 5.0.git
• For version 4.1

Beware of the many orphaned operators which haunt our attic directories and obscure branches.

User and developer manual (pdf)

Publications related to FloPoCo

Publications describing FloPoCo or FloPoCo operators

Publications citing FloPoCo

Authors and credits

FloPoCo is managed by Florent de Dinechin (contact: Florent.de-Dinechin at insa-lyon.fr) and Martin Kumm (contact: martin.kumm at cs.hs-fulda.de).

Developers: Hatam Abdoli, Sebastian Banescu, Louis Besème, Andreas Böttcher, Nicolas Bonfante, Nicolas Brunie, Romain Bouarah, Victor Capelle, Jiajie Chen, Maxime Christ, Caroline Collange, Quentin Corradi, Florent de Dinechin, Orégane Desrentes, Jérémie Detrey, Antonin Dudermel, Fabrizio Ferrandi, Nicolai Fiege, Luc Forget, Martin Hardieck, Valentin Huguet, Kinga Illyes, Matei Iştoan, Mioara Joldeş, Johannes Kappauf, Cristian Klein, Marco Kleinlein, Kilian Klug, Martin Kumm, Jonas Kühle, Keanu Kullmann, Louis Ledoux, Jean Marchal, Antoine Martinet, Konrad Möller, Raul Murillo, Annika Oeste, Bogdan Pasca, Bogdan Popa, Xavier Pujol, Guillaume Sergent, Viktor Schmidt, David Thomas, Radu Tudoran, Alvaro Vasquez, Anastasia Volkova

Some of FloPoCo's operator code is based on FPLibrary and HOTBM code by Jérémie Detrey.

The following people have contributed to FloPoCo in some way (bug reports, porting, etc): Greg Davey, Mariusz Grad, Daniele Mastrandrea, Pedro Echeverría Aramendi.

FloPoCo uses Sollya, ScaLP, WCPGlib, and relies heavily on GMP and MPFR.

FloPoCo is essentially developed using Free Software. Special thanks to the NVC project for providing us a perfectly useable VHDL simulator.

The following support is gratefully acknowledged

• Altera through the donation of a Stratix IV development kit
• Stone Ridge Technology through the donation of a RDX-11 board
• Xilinx through the donation of two Zedboards
• ANR for funding some of this work through the TCHATER, MetaLibm and Imprenum projects
• DFG for funding the project "Optimization of Multipliers for Reconfigurable Logic", (project number 426369132)